چاپ
CV
IAUN
Islamic Azad University, Najafabad Branch

 1- Personal Information  
First Name : Mehdi
Last Name : Dolatshahi
E-mail : dolatshahi@iaun.ac.ir
Work Address : Islamic Azad University, Najafabad Branch, Esfahan
Academic Rank :Assistant Professor


 2- Education Background  
Academic Degree Education Field University Country Year
B.Sc Electronic Engineering - IRAN -
M.Sc Electronic Engineering - IRAN -
Ph.D Electronic Engineering Tehran Science and Research Branch, Islamic Azad University IRAN 2011


 3- Educational Experience  
Row Specialized Courses Taught Degree
1 مدارهاي مخابراتي کارشناسي
2 طراحي VLSI کارشناسي ارشد
3 طراحي مدارات مجتمع پيشرفته کارشناسي ارشد
4 طراحي مدارات VLSI پيشرفته کارشناسي ارشد
5 طراحي سيستمهاي مطمئن و آزمون پذير کارشناسي ارشد
6 الکترونيک 3 کارشناسي
7 طراحي مدارات مجتمع خطي کارشناسي ارشد


 4- Research Interests  
Row Fields of Investigation and Specialized
1 Analog and Digital Integrated Circuits Design
2 VLSI Circuits and Systems Design
3 CMOS Optical Communications Circuit Design
4 CMOS Circuit Design Optimization using Artificial Intelligence
5 Fault Tollerance and Testability In VLSI Circuits
6 Low-Power/ High-Speed/ Low-Voltage IC Design
7 Hardware Implementation of CMOS Neural Networks and Fuzzy Systems


 5- Research Activities    5-1) Paper Published in Journals  
Row Article title Journal Name Year Volume Article Printed Pages
1 Design and Simulation of a Fully Integrated, Low-Power, 2.5Gb/s Optical Front-End Majlesi Journal of Telecommunication Devices (MJTD) 2018 7-4 161-169
2 An Ultra-Low-Power and Full-Swing Full Adder Cell Majlesi Journal of Telecommunication Devices (MJTD) 2018 7-4 123-130
3 A 5Gbps, Inductor-less Transimpedance Amplifier for Optical Communications using 0.18μm CMOS Technology Majlesi Journal of Telecommunication Devices (MJTD) 2018 7-3 95-101
4 A Low-Power CMOS Optical Communication Front-End Using a Three-Stage TIA for 5Gb/s Applications Majlesi Journal of Electrical Engineering 2017 11-4 11-19
5 Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor International Journal of Engineering and Manufacturing 2016 6-1 1-9
6 Design Optimization of a Low-Power CMOS OTA using gm/Id Methodology Indian Journal of natural sciences 2015 5-30 8254-8261
7 Designing and Simulating a New Full Adder with Low Power Consumption International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 2015 4 1184-1195
8 A New Low-Power CMOS 5Gb/s Optical Receiver for Optical Communication Systems Indian Journal of natural sciences 2015 6 9018-9031
9 A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm International Journal of VLSI design 2015 6-6 1-9
10 A low-power multi-mode and multi-output high-order CMOS universal Gm-C filter ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2014 79 95-104
11 A new systematic design approach for low-power analog integrated circuits International Journal of Electronics and Communications (AEÜ), ELSEVIER 2012 66 384-389
12 Design and Simulation of a New Sample and Hold Circuit with Resolution of 12-Bit and a Sampling Rate of 1 GS/s Using a Dual Sampling Technique Journal of Intelligent Procedures in Electrical Technology (JIPET) 2018 9-34 3-10
13 Line Sensitivity Enhancement of Low Power Voltage Reference Circuits Using a Novel Two Stage Structure in Subthreshold Tabriz Journal of Electrical Engineering 2018 48-3 1263-1271
14 Design of a 12-Bit 200MS/S CMOS Sample-and-Hold Circuit Journal of Intelligent Procedures in Electrical Technology (JIPET) 2014 18 53-60
15 Design of a Low-Power Universal Gm-C Filter in Sub-Threshold Region Journal of Intelligent Procedures in Electrical Technology 2013 4-15 3-10
16 A Low-Power CMOS Trans-Impedance Amplifier for 2.5 Gb/S Optical Communication Systems Journal of Intelligent Procedures in Electrical Technology 2013 4-13 29-34

 5-2) Papers Presented at the Conference  
Row Article title Conference Name Conference Location Year
1 A 274µW, Inductor-less, Active RGC-Based Transimpedance Amplifier Operating at 5Gbps 27th Iranian Conference on Electrical Engineering (ICEE2019) Yazd 2019
2 A new 10 Gb/s optical receiver using active inductor in 90 nm CMOS technology 26th Iranian Conference on Electrical Engineering (ICEE2018) Mashhad 2018
3 Automated Design And Optimization Of A CMOS OTA Using Geometric Programming 26th Iranian Conference on Electrical Engineering (ICEE2018) Mashhad 2018
4 Increasing the efficiency of NOC routing algorithms based on fault tolerance measurement method 2018 International Young Engineers Forum (YEF-ECE) Portugal 2018

 5-3) Completed Research Plans  
Row Title Responsibility Project Kind

 5-4) Compilation and Books  
Row Title Compilation Kind Compilation Publishing Date Publisher

 5-5) Initiative, Innovation and Invention, and Valuable Asrbdy  
Row Title Registration Place Reference Confirmed Date

 5-6) Awards and Honors  
Row Institution Title Festival Date Reference Award Announcement

 5-7) Lecturer Of Workshop  
Row Title Date
1 Analysis and Design of Integrated Circuits and Systems using HSPICE -Preliminary 29/04/2014
2 Design of Integrated Circuits and Systems using HSPICE -Advanced 02/12/2013
3 The Application of HSPICE in Integrated Circuits Research and Development 16/12/2013


 6- Executive Experience  
Row Title Executive Year
1 Department Chair of Research affairs 2011
2 Scientific commitee- 3th national conference on electrical e 2011
3 Director in General of Research Affairs 2015
4 International Symposium on Computing in Science 2010